1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus having an improved refresh capability.
2. Related Art
A DRAM (dynamic random access memory) is a typical volatile memory device for a semiconductor memory apparatus. A single memory cell in DRAM includes a cell transistor and a cell capacitor. The cell transistor controls access to the cell capacitor, and the cell capacitor stores charge in response to the data. That is, data is identified as high level data and low level data according to the amount of charge stored in the cell capacitor.
Meanwhile, since charge is introduced to or discharged from the cell capacitor through a leakage current in the memory cell of DRAM, it is necessary to periodically store the stored data. Such a periodic operation for accurately maintaining data is called a refresh operation.
DRAM typically performs refresh operations 4K or 8K times per 64 ms, and such refresh cycles are fixed. A memory unit of DRAM is divided into a plurality of memory banks and the refresh operation is typically simultaneously performed for all memory banks. Therefore, since a very large peak current is generated when all memory banks are simultaneously activated during the refresh operation, instantaneous power consumption is very large which may cause problems in operation stability due to the excessive peak current.